A Medical Electronics Manufacturing Fall 1997 Feature

ELECTRONIC PACKAGING

Advanced Electronic Packaging Techniques Enhance Function, Performance, and Portability

Nicholas Brathwaite and Kangsen Huey

Alternative packaging technologies are moving to the forefront as devices require increased portability and performance.

Electronic packaging and assembly technologies are growing more complex, and the rate of technological change is accelerating. While surface-mount technology (SMT) is now considered the most mature technology, new developments continue to extend its capabilities to higher levels. Traditional leaded SMT components are still very popular because they tend to be less expensive than other microelectronic packages while offering a vast array of readily available choices. However, as device complexities increase and I/O counts escalate, leaded SMT packages are becoming larger, with lead pitches shrinking as low as 0.3 mm. As a result, alternative packaging and assembly technologies are gaining in prominence, particularly ball-grid arrays, chip-scale packages, chip-on-board packages, and flip-chip assemblies. In many cases, these newer technologies can increase the portability and performance of finished devices while trimming overall assembly cost. In addition, many can actually help to reduce time-to-market.

In chip-on-board techniques, wire is bonded directly onto a board.

Ball-Grid Arrays

With leaded SMT packages, specifically the plastic quad flat pack (QFP), assembly defect rates have stabilized at 50­200 dpm (defects per million) for devices with a lead pitch of 0.5 mm and at 250­600 dpm for devices with a lead pitch of 0.3 mm. QFP is the most popular SMT package in use today, with over 80% of SMT components employing this format. The QFP is assembled with a lead frame and encapsulated with molding plastic. It has gull-wing leads around its peripheral edges. Pin count can go as low as 8 pins for a dual in-line package to as high as 304 pins for the QFP. Size is determined by the space required for peripheral pins, so, for example, a 304-lead, 0.5-mm-pitch QFP requires a package size of 40 x 40 mm. Therefore, alternative package types are needed to meet the demand for increased I/O count with reduced package footprint.

Typical chip-on-board design.

One such alternative, the ball-grid array (BGA), is already starting to dominate the SMT field. Industry analyst Dataquest Inc. (San Jose), forecasts that BGAs will account for 4.8 billion of the 68.5 billion packages that will be produced in the year 2000. BGA technology has successfully addressed the shortfalls of QFPs concerning size reduction, I/O limitation, and assembly yield. These packages not only provide a significant increase in board density, but are easier to handle, more robust, and more easily manufactured than fine-pitch QFPs.

Miniaturization provides increased functionality per unit area, with bare die assembly providing the best package density.

The BGA is a semiconductor component assembled on either a plastic laminate or ceramic substrate instead of a lead frame. For I/O connections, the BGA uses an area array of I/O pads at the bottom of its substrate. Ball pitch is 1.5, 1.27, or 1.0 mm­much larger than the QFP's 0.65-, 0.5-, or 0.3-mm pitch. A typical 27 x 27-mm BGA at 1.27-mm ball pitch has 225 I/Os and is much smaller and easier to assemble than the comparable 208-lead, 28-mm QFP, which requires a 31.2 x 31.2-mm footprint and a lead pitch of 0.5 mm. However, BGAs cannot be visually inspected by the assembly technician, nor can individual leads be reworked like the peripheral leads of a QFP. Therefore, as with the QFP, BGA packaging raises a whole new class of issues.

Breakthroughs have been made over the years, but successful BGA assembly can only be achieved by excellent and consistent process controls, which are not always present in traditional PCB assembly operations. For example, boundary-scan capability built into the silicon die can electrically detect interconnection opens and shorts without x-ray inspection, but cannot tell the quality of the solder joints. Furthermore, cross-sectioning and x-ray inspection are costly and time-consuming. Total process control has emerged as the only solution to ensure the quality of BGA assembly, which offers far too much benefit to be discounted as a viable packaging method. A well-developed BGA assembly process can produce a steady yield as low as 10­20 dpm.

The future of BGA packaging depends on the successful resolution of three crucial issues. First, process engineers must develop a BGA manufacturing procedure that is capable of maintaining a high manufacturing yield. Second, they must develop a manufacturing procedure that can sustain the overall quality of BGA assemblies across an extended period of time. And lastly, they must characterize and qualify the BGA assembly process for long-term reliability.

Developing the capacity to produce high-quality BGAs requires a heavy initial investment of time and money; as a result, smaller manufacturers have been effectively prevented from employing the technique. However, as the cost of BGA component manufacture drops and more IC devices become available in the BGA format, BGA packages will probably come to dominate the field for high-pin-count devices.

Chip-Scale Packages

Another technique developed to extend the reach of surface-mount technology is the chip-scale package (CSP). Chip-scale packages have the smallest outline among all packaged parts and represent an intermediate step between BGAs and flip chips. CSPs are typically only 1.2­1.3x larger than the bare die itself, and some CSPs are essentially shrunken BGAs. The external I/O grid array of a CSP is typically at a pitch of 0.5­1.0 mm, which is smaller than that of a BGA but much larger than a flip chip's fine pad arrays. CSPs are the smallest packages outside of bare-die assemblies and are easier to accommodate on existing setups capable of BGA assembly.

The CSP technique is gaining attention thanks to its impressive size reduction. It is already being used extensively in some consumer products for miniaturization. It is likely that the earliest CSPs available for the public will be low-pin-count, high-performance devices like Flash memories and Static RAMs.

Chip-On-Board Technologies

Complementing the SMT processes are the bare-die processes, in particular the chip-on-board (COB) and flip-chip techniques. In the COB assembly process, a bare (unpackaged) semiconductor is attached directly onto a PCB, wire bonded, and then encapsulated with a polymer. For many applications requiring miniaturization, COB assembly can be the most cost-effective packaging option. This inexpensive and mature technology readily accommodates miniaturized low-profile assemblies. It also offers high packaging density, low packaging cost, and fast signal speed because the dies are wire bonded directly onto a board. Of all the high-density packaging technologies involving bare-die assembly, COB, which can save board space without adding substantial risk in cost or reliability, is the most promising.

High-density multichip module with silicon substrates.

The COB is normally assembled along with other SMT components on the same PCB to take advantage of both technologies. The COB uses peripheral fan-out pads on the bare IC, so most bare dies designed for BGA and QFP packaging can be used directly for COB assembly. The peripheral fan-out allows circuit boards to be routed with 0.005-in. line and space rules, which are widely available and relatively economical. The current PCB fabrication technology becomes a bit more difficult for COBs when used with multiple ICs having more than 200 pins each.

A ball-grid array process implementation vehicle using a six-layer board.

COB technology has not yet achieved widespread use, although the assembly processes and infrastructure are indeed mature­in fact, the same basic technology is used to package over 90% of all integrated circuits. Still, the die-attachment, wire-bonding, and dispensing equipment must be added to the standard SMT line to enable COB production, and most manufacturers have not yet made the additional investment. Many manufacturers also hold the inaccurate perception that a bare-die assembly absolutely requires a known-good-die (KGD), which is a fully tested bare die with quality levels equivalent to its packaged counterparts. However, if the bare-die component is fabricated with mature semiconductor processing technology­like most logic devices­it ought to have a very high fabrication yield, in the high 90% range. By eliminating the added costs related to component packaging and additional package testing, COB can very well be cheaper than the packaged parts, even when the scrap rate due to bare-die failure is accounted for. Therefore, for most COB assembly, there is no need to add the KGD process to the bare die, which adds cost to the material, but has little benefit.

Flip-Chip Technology

Another bare-die assembly process is the flip-chip technique, in which the component is attached face down directly to a substrate with solder bumps or z-axis conductive polymers. First developed by IBM, flip-chip assembly nearly eliminates all the packaging area that is not occupied by the die itself, resulting in the smallest footprint and the lowest profile. Of all the techniques discussed, flip-chip assembly offers the highest packaging density, and for some applications can also be the least expensive option. In general, underfill is used for full-array flip chips and conductive adhesive is used for peripheral-array flip chips to improve thermal conduction and solder-bump reliability. With the shortest interconnection length, flip chips have the lowest interconnect inductance and resistance, resulting in the highest performance among all packaging technologies. Thus, for high-speed uses with data rates from several Mbit to several Gbit per second, flip chip is the preferred­if not the only­assembly option.

In general, flip chips can use either grid arrays or peripheral pads for I/O connection at pitches between 0.1 and 0.65 mm, but most are used at an area-array pitch of 0.2­0.3 mm. In the past, flip chips designed with a small pad pitch required very fine line routing and forced manufacturers to use expensive substrates other than laminated PCBs. With improved substrate technologies­such as fine-geometry ceramic substrates, laminated PCBs with buildup structures, and flexible circuits­economical flip-chip applications are becoming more feasible.

In rare cases, low-pin-count devices with area-array pitch of 0.5 mm or more can employ existing SMT assembly equipment for flip-chip assembly, which can be the most cost-effective assembly method. However, for typical high-pin-count flip-chip assemblies, manufacturers need additional processes such as wafer bumping and specialized equipment such as pick-and-place and under-fill systems.

Opponents of bare-die assembly techniques have used the limited availability of KGD to scare OEMs away from COB and flip-chip assembly. Although KGD will certainly extend the use of bare-die assembly technologies, it is generally not necessary for many applications involving only one or two bare dies assembled on a board. Manufacturers must consider the maturity of the design, circuit density, complexity, testability, and yield history of the die to determine whether KGD is really necessary.

Conclusion

Miniaturization is currently one of the most important requirements for next-generation product developers in every industry, from computers to medical devices. In addition to higher levels of reliability, customers are demanding greater portability, increased functionality, and improved performance.

With BGA fast becoming a major part of mainstream SMT assembly, and CSP not far behind, existing surface-mount assembly technology will certainly survive for a while. However, the trend toward miniaturization is already forcing circuit-board designers and assemblers to push design rules by placing components closer together than ever, increasing SMT pin counts and reducing pitch. Soon, OEMs will require some sort of bare-die assembly to complement new product designs in order to increase density or cut costs.

Nicholas Brathwaite is vice president, Advanced Packaging and Engineering Services, and Kangsen Huey is manager, Technology Marketing, for Flextronics International Ltd. (San Jose).