Medical Device Link.

Originally Published MEM Spring 2004

ASIC TECHNOLOGY

Low-power, high-voltage devices support higher functionality in less space while minimizing power loss.

Bob Klosterboer

With technological advances, implantable medical electronic devices naturally offer an increasing number of features crammed into a smaller space. These two conflicting requirements—greater functionality and greater miniaturization—are driving the demand for a new class of mixed-signal silicon chips specifically designed for implantable medical applications.

Implanted application-specific integrated circuits (ASICs) must handle other sets of divergent requirements as well. A medical ASIC may be required to operate on a few volts in order to support extended battery life, yet still be capable of delivering high-voltage signals when needed, as, for example, a pacemaker pacing signal. Or the ASIC may be completely isolated within the body, yet need to be able to communicate with the outside world.

To answer these apparently contradictory system-level requirements, medical device designers are employing fewer discrete components. Instead, manufacturers are developing mixed-signal ASICs manufactured using sophisticated complementary metal-oxide semiconductor (CMOS) process technologies.

Cutting Power Losses

Keeping power losses to an absolute minimum is the primary goal of any designer who is building a battery- powered ASIC, particularly one to be incorporated in an implanted medical device. Power is the product of the IC supply voltage and the current consumed by the IC during operation. CMOS is an inherently low-power process, but even so, electrical current must be carefully managed. Current is consumed in one of three ways in any CMOS circuit: as cross-conduction current (also known as short-circuit through current), as dynamic current, or as static leakage current.

Figure 1. Cross-conduction current flows through a stacked pair of CMOS transistors as the logic gate, an inverter, changes state. (click to enlarge)

Cross-conduction current is consumed when a stacked pair of transistors in a digital logic gate switches its binary logic state—changes, say, from a logic one to a logic zero. During that switching time, the complementary n-channel and p-channel transistors are momentarily both turned on, allowing a brief transient current to flow (see Figure 1).

A simple formula that describes the effect of cross-conduction current on power consumption is

P_TC = V_DDf_clk(t_RI + t_FI),

where P_TC is the power consumption, V_DD is the power supply voltage, f_clk is the frequency at which the stacked pair of transistors changes state, t_R and t_F are the rise and fall times of the input signal, and I is the cross-conduction current that flows through the stacked transistors as they change state. Although the transistors are on simultaneously for only a tiny fraction of the clock cycle, the amount of current that flows can be quite large. Only the small on-resistance (R_DS in Figure 1) of the transistors limits the magnitude.

Dynamic power dissipation is the cumulative effect of thousands of stacked transistor pairs changing state as the digital logic performs its functions in strict accordance with a controlling clock. The stacked pair of transistors is the most, common circuit in any CMOS design that contains even a small amount of digital logic. The brief pulses of current, multiplied by the number of switching logic gates on the ASIC, can quickly become large volumes of current that consume energy on every clock signal. That is because every time a stacked pair of transistors changes state, a small amount of parasitic capacitance must be charged or discharged.

Every capacitor, no matter how small, is an energy storage element. Tiny localized quantities of capacitance abound in every IC, ranging from the parasitic capacitances on interconnect wires to the gate capacitances of connected transistors. Larger amounts of capacitance exist in the off-chip circuit-board traces. Added together, these can constitute quite a large load capacitance. The current needed to charge and discharge this capacitance will also be large.

Dynamic current can be characterized by the following simple formula:

P_Dynamic = C_LV²_DDf_clk

Here, C_L is the load capacitance, V_DD is the power supply voltage, and f_clk is the clock frequency.

Dynamic and cross-conduction power losses can be controlled by reducing the factors involved. These factors are largely under the control of the IC designer, who can decide on means to reduce the power supply voltage, load capacitance, and rise and fall times, and determine how to slow or stop the clock frequency.

Static power dissipation, however, is the form of power loss that bedevils CMOS process developers, because it includes a parameter that cannot be easily controlled by the designer. Static current is described by

P_Static = I_leakV_DD ,

Figure 2. A normalized graph showing that leakage current increases as the transistors get smaller. (click to enlarge)

where V_DD is the power supply voltage and I_leak is the degree to which the annoying tendency of CMOS transistors to allow very small amounts of current to flow even when the transistors are turned off manifests itself. As shown in Figure 2, the smaller a transistor gets, the more leakage current tends to flow.

Static current leakage can be controlled by removing the voltage from the portions of the IC that are not being used. But because that is not always an option, process engineers compensate by changing the transistor's physical and electrical characteristics.

New Process Technologies

The usual response to the imperative of reducing power losses is to lower the supply voltage, since that tactic brings a square-law improvement in dynamic power losses as well as gains in cross-conduction and static power loss. For a battery-powered ASIC, a low supply voltage dovetails nicely with the twin ideals of minimizing the number of battery cells and keeping the ASIC operating for as long as possible as those cells slowly lose energy. Figure 3 expresses as a graph how a 10:1 reduction in dynamic power can be obtained in conjunction with a 3:1 drop in supply voltage. Essentially, a reduction in power from x to one-tenth of x results from a change in supply voltage from y to one-third of y.

Nothing comes for free, however. Lowering the supply voltage raises a couple of concerns.

Figure 3. A 10:1 improvement in power dissipation comes in conjunction with an approximate 3:1 reduction in voltage. (click to enlarge)

First, while discrete-state digital circuits can function well at reduced supply voltages, analog circuits do not scale as well. By virtue of operating on binary information, digital circuits offer a wide noise margin and are inherently resistant to all but the most disruptive of events. Analog circuits, however, must operate on a continuous range of information. Their noise margin is much smaller relative to signal strength. In addition, the fundamental transistor properties change as the supply voltage drops close to the transistor's threshold voltage, the point at which the transistor can be turned on and off.

Second, medical ASICs still need to interface with the outside world, often at voltages that are several times higher than the operating voltage of the ASIC. To avoid physically damaging the IC itself and to solve the problem of the conflicting requirements of low power and high voltage most simply, two different chips have to be developed. The natural divide is to place the low-voltage digital portion in one chip and to have the second IC contain the high-voltage analog circuits and output drivers.

However, the use of two separate chips often results in additional input/output (I/O) pins, many of which are needed to support chip-to-chip communication. The extra circuit board traces and longer path lengths increase the off-chip load capacitances that must be charged and discharged by larger I/O drivers. That, in turn, leads to necessary additional power consumption.

Multiple chips also consume more board space and often run afoul of footprint restrictions. Therefore, both power dissipation concerns and the severe size constraints of medical devices force designers to meld the low-voltage and high-voltage circuits. As a result, new manufacturing technologies have had to be developed that allow these disparate types of circuit to coexist.

Figure 4. A photomicrograph of a trench barrier. (Source: AMI Semiconductor.) (click to enlarge)

The need for coexistence can be addressed by means of a special isolation technique that physically separates low-voltage circuits from high-voltage devices such as those necessary for pacemaker or defibrillator output drivers. It is known as deep-trench isolation. The goal is to protect low-voltage transistors from the electric-field effects of voltages that can be 10 to 30 times higher. Figure 4 shows a trench in cross section.

The trench barrier is added to a modified version of a CMOS process. Low-voltage transistors as small as 350 nm can be manufactured in a deep-trench process. The small transistor size allows sophisticated microprocessor cores and memory to be packed into a compact space. These low-voltage devices are tucked into pockets that protect them from high electric fields. Meanwhile, the high-voltage transistors that are capable of interfacing with pacer leads or with other medical devices may be added outside the pocket areas.

Low-Power Radio Communications

Interfacing to the outside world is another problem altogether, particularly with respect to implanted devices. In many such applications, newly developed low-power radio-frequency (RF) transceiver ICs are at the forefront of a broad trend to add wireless communications to implantable medical electronics. RF technology is expected eventually to encompass a wide variety of devices, including cardiac rhythm management devices, implanted glucose meters and insulin pumps, vascular blood pressure monitors, incontinence control devices, and neuromodulators.

This trend was enabled in 1999, when the Federal Communications Commission set aside the Medical Implant Communications Service (MICS) frequency band between 402 and 405 MHz specifically for wireless data communications between implanted medical devices and external equipment. The band of 402–405 MHz was chosen for several reasons. First, a low-power transmitter and antenna designed specifically for it can be made small enough and still provide excellent performance over a 6-ft transmission range. Second, the frequency range does not pose an interference risk for other radios operating in the same band. And finally, the frequencies in the MICS band have propagation characteristics that are conducive to the transmission of radio signals within the human body. The MICS band additionally is compatible with international frequency bands for implantable devices.

Chip-based RF transceivers employ several techniques to keep the power consumption of a MICS-band radio as low as possible. Since the transmission distance need be no more than a few feet, a short radio range provides the first measure of power savings by keeping the transmitter power requirements low. A low data rate means that the power-hungry transmitter circuits can be powered off when not required.

Figure 5. Duty-cycling the RF receiver provides continual monitoring while consuming little power. (click to enlarge)

Another technique is to power-down the receiver circuits periodically to conserve power further (see Figure 5). At regular intervals, the radio awakes from a sleep state, looks for an inquiring RF signal, and shuts down again if no signal is found. This periodic polling of a radio frequency provides continual monitoring yet consumes very little power.

The receiver power-up/power-down cycle can be completed in less than 100 microseconds. This makes it possible to obtain very low average power consumption while monitoring the MICS channel for transmitted messages. Both power-down techniques require a rapid-start oscillator that can wake up the receiver and, if needed, the transmitter in an extremely short time.

Sophisticated transceivers contain base-band clock and data recovery (CDR) circuits that postprocess the demodulated incoming data stream to produce both a sampled data bit stream and a clock signal. The CDR technique improves transmission reliability by synchronizing the data processing clock with the incoming data. Therefore, power is not wasted through the retransmission of error-corrected data.

Figure 6. A block diagram of a low-power MICS radio. (click to enlarge)

Both the amplitude shift key/on-off shift key (ASK/OOK) and frequency shift key (FSK) methods are popular modulation schemes in narrow-MICS-channel applications. Twin independent receive channels help improve the reliability of MICS transmissions so that power is not wasted on retransmissions (see Figure 6).

Mixed-Signal Technology

Mixed-signal ASICs often incorporate analog interface electronics, such as analog-to-digital (A/D) convertors and RF transceivers, and combine them with a digital computational core in the form of a microprocessor or digital signal processor (DSP). A wireless medical sensor is a good example of such architecture; there, the computing power of digital logic is mated with the real-world sensing capability of analog circuitry on a single chip. Because power consumption is a concern, many medical sensors are designed simply to transmit amplified analog signals to another application for further processing.

However, more-sophisticated medical sensors are capable of digitizing the amplified analog signal by means of a low-power but high-resolution A/D convertor. Digitized sensor signals provide the advantages of being more immune to noise and of being transmitted easily over wires or wirelessly using error-correcting protocols. In addition, digitized signals can be filtered and equalized to remove imperfections in the original signal.

An application example would be a hearing aid. Analog sensors capture the electrical impulses that represent sound waves, amplify them, and convert them into digital signals. The signals are filtered and processed by a 16-bit DSP to remove noise and adjust volume and are then converted back into analog sound waves. All of the signal processing must be done on a chip that is no larger than 10 mm2 so that the hearing aid itself can fit comfortably into the ear canal.

Conclusion

Low-power/high-voltage processes and low-power radio technology augmented by mixed-signal know-how can provide a variety of ASIC solutions for medical device manufacturers trying to cope with the challenges of packing more features into less space. The development of trench isolation techniques to separate the low-voltage circuits from the high-voltage transistors has made it possible to accommodate the power conservation requirements of a battery-powered implantable device that must be able to interface with the outside world.

Combining low-power radio technology with analog sensors and a digital microprocessor core promises to improve access to patients' physiological data and enable medical teams to provide better patient care. Battery-life requirements will always push the demand for low-power medical IC solutions. But the mounting pressure to cut medical device costs is expected to be the future driver for advanced mixed-signal ASIC technology, while at the same time medical device designers continue to introduce additional new features into ever smaller spaces.

Bob Klosterboer is senior vice president for integrated mixed-signal products at AMI Semiconductor (Pocatello, ID).

Copyright ©2004 MX